پروطه وریلاگ ساخت cpu اسان با برنامه زایلینکس

A Processor with Von NeumannMemory in Two ModesIn this document, we describe a processor with two modes: mode 1 and mode 0. Thisprocessor uses Von Neumann memory architecture in both modes, where both data andinstructions are stored in the same memory space.1. Single Memory Storage: Both program instructions and data share the same memoryresources.2. Limitations: memory access is a bottleneck for performance.Mod 1:The table below illustrates the opcode instructions used in this processor.Opcode Description ExampleInstruction Example Result0000Add two registers andsave the result in the******* R\[1\] ← R\[1\] + R\[2\]1st reg0001Subtract two registersand save the result inthe 1st reg******* R\[1\] ← R\[1\] − R\[2\]Multiply two registersand save the 8 leastsignificant bits of******* result in R\[1\], and theR\[2\] ← (R\[3\] ∗ R\[4\])\[15 : 8\]R\[1\] ← (R\[3\] ∗ R\[4\])\[7 : 0\]8 most significant bitsin R\[2\]0011And two registers andsave the result in the1st reg******* R\[1\] ← R\[1\]&R\[2\]Or two registers and0100save the result in the******* R\[1\] ← R\[1\] | R\[2\]1st reg0101Xor two registers andsave the result in the1st reg******* R\[1\] ← R\[1\]ˆR\[2\]Move the value of the01102nd register to thefirst reg******* R\[1\] ← R\[1\]0111Move the value of the2nd operand to thefirst register******* R\[1\] ← 141000Shift the first registerleft as much the value******* R\[1\] ← R\[1\] << R\[2\]of the 2nd register******* Load from memory ******* R\[0\] ← Mem\[16\]1011 Shift the first registerright as much thevalue of the 2ndregister******* R\[1\] ← R\[1\] >> R\[2\]Save to memory Mem\[16\] ← R\[0\]On the rising edge of the clock, an instruction is sent from memory to the CPU.The CPU receives these instructions on the falling edge of the clock and executes theoperations.Some operations require sending data back to the memory.To achieve this, it needs to activate an Enable signal connected to the memory during thesame clock edge, allowing the data to be sent to memory.The memory will receive the data when this Enable = 1.Now, how do we determine where to store the data?Before the STORE instruction is sent from memory to the CPU, the address is alreadyincluded in the instruction.Thus, the CPU must keep this address beforehand to store the data at the correct locationduring the return path.The primary challenge in this mode is ensuring proper synchronization between thecomponents.In the CPU, there are 16 registers, each 8 bits wide. Why are they 8-bit?Refer to the last two instructions, which involve memory operations.Since both instructions and data are stored in the same memory, the memory size mustalign with the length of the instructions, which is 12 bits.But this raises a question: when sending 8-bit data to memory, what happens to theremaining 4 bits?The solution to this problem is simple. Think about it carefully. These kinds of challengesare common in projects and require attention to detail.Memory Size:The total memory size is flexible, but it must meet the following conditions:1. 2. 3. It must be a power of 2.Avoid making it excessively large to prevent unnecessary complexity.A size like 64 seems reasonable and manageable.Simplification for Testing:To make testing easier, include the following code in your memory module:𝒊𝒏𝒊𝒕𝒊𝒂𝒍 $𝒓𝒆𝒂𝒅𝒎𝒆𝒎𝒃("𝒓𝒂𝒎𝒔𝟐𝟎𝒄. 𝒅𝒂𝒕𝒂"\_, 𝒎𝒆𝒎𝒐𝒓𝒚, 𝟔𝟑, 𝟎);You also need to create a file in your project folder with the extension .data.For example, name the file rams\_20c.data.The range 63, 0 in the code depends on your memory definition.In this .data file, you can input 12-bit instructions, each on a new line.For example, here’s a Fibonacci sequence program that calculates the value 8:Fibonacci Program (12-bit Instructions for .data File):*******Module Setup:You need a main module that connects your CPU and memory.The inputs to this module are clock and mode.In your testbench, initialize the clock and set the mode appropriately:1. Start the clock.2. Set the mode to 1.Steps for Testing:1. 2. 3. Copy the above instructions into the rams\_20c.data file.Simulate the code using your testbench.Ensure you set the mode to 1 during the simulation.Mod 0:One of the challenges in computer science is balancing between complex processingwith short instructions and simple processing with longer instructions. Mode 0specifically addresses this concept. Here, we work with simpler instructions, but theyrequire more effort because they are very basic.In this mode, memory contains two types of data:1. 2. Instructions, which start with 0.Data, which start with 1.Key Characteristics of Mode 0:1. Energy Efficiency:To reduce CPU energy consumption, only three registers are used: Register 1,Register 2, and Register 3.2. Supported Instructions:o Addition: Performed using Registers 1 and 2; the result is stored in Register 3.o Subtraction: Similar to addition, but performs subtraction instead.o Jump: Two types are supported: upward jump and downward jump,depending on how you define memory in your test file.o Memory Writing: Data can be written to memory only from Register 3 orRegister 2, each with a distinct instruction.3. Memory Data Handling:If the memory points to a data value, it sends that data directly to the CPU. (intoRegister 1 or Register 2) based on the second most significant bit of the data.Example InstructionsInstructionType Operation Addition Add values fromRegisters 1 and 2 0000\_\_XXXXXXXX SubtractionExample Used Subtract value inRegister 1 fromRegister 2NotesR\[3\] ←R\[1\]+R\[2\]0001\_\_XXXXXXXX R\[3\] ←R\[2\]-R\[1\]Write value fromWrite toRegister 2 to******* \_\_Memory R2Write value of R2 to addres 20depend on test file.memoryWrite toMemory R3Write value fromRegister 3 tomemory******* \_\_Write value of R3 to addres 21depend on test file.I ( as pointer in momry) to IJump(Downward)Jump to a laterinstruction 0100\_\_*******Downward with value 20depend on test file.Jump(Upward)Jump to an earlierinstruction 0101\_\_*******I ( as pointer in momry) to IUpward with value 20 dependon test file.Load data fromLoad Data R1memory to Register10\_\_******* R\[1\] ←11Load Data R2Load data frommemory to Register211\_\_******* R\[2\] ←1You need to implement Mode 1 first, and writing Mode 0 won't be difficult afterward.The main point is that you should be able to switch the mode without altering thestructure, the number of input and output bits in memory, and the CPU (including thememory and CPU registers).In short, you should change the test file and set the mode to 0 in the testbench. The codemust still be able to run the simulation successfully.Fibonacci Program (12-bit Instructions for .data File inmode 0):*******Bonuses:1. Parameterize Data Sizes:Ensure that the size of instructions, data, and registers can be handled usingparameters. The initial values of these parameters should be based on thedocumentation.2. Sum and Average in Two Modes:Implement functionality to sum 8 numbers together and calculate their average inboth modes.