104950 - کیدنس

سلام من یک پروژه تحقیقاتی دارم؛ آیا می‌توانید آن را با استفاده از Cadence انجام دهید؟ Design is a 12-bit, 1 GS/s continuous-time pipeline ADC in 65 nm CMOS (Cadence only). Architecture “shape”: Differential input → CT pipeline stages (no S/H) → backend ADC → digital FIR-based error correction → 12-bit output. Each pipeline stage consists of: * Continuous-time residue amplifier (OTA-C / active-RC, not switched-cap) * Sub-ADC (1.5-bit with redundancy) * Fast DAC feedback for residue generation There is no front-end sample-and-hold. Sampling is implicit through continuous-time operation with clocked quantizers, suitable for 1 GS/s. Digital error correction is FIR-based, not simple bit alignment: * FIR filter compensates inter-stage gain error, finite bandwidth, and timing skew * Enables high ENOB at 1 GS/s * Implemented and verified in Cadence (behavioral/Verilog-A) Deliverables: * Full Cadence schematics (all CT stages + backend) * Transient + FFT (SNDR/ENOB @ 1 GS/s) * INL/DNL, PVT, Monte-Carlo * Power & FoM * Complete report with architecture, equations, FIR correction explanation, and results چهار ماه #ونیکو